1. Field of the Invention
The present invention generally relates to optimization of integrated circuits. More specifically, the invention relates to mechanisms and techniques for optimizing the power used in an integrated circuit.
2. Description of Related Art
Various aspects of an integrated circuit are generally optimized to improve the efficiency of the integrated circuit. For example, reducing the power consumed by various components of a circuit can reduce the amount of heat generated and improve the performance of the integrated circuit. However, conventional techniques and mechanisms for optimizing power used in an integrated circuit are limited. For example, multipliers in a circuit design are often implemented in a field programmable gate array (FPGA) exactly as the circuit designer specifies them. No optimization technique for minimizing the power used by the multipliers is implemented.
Therefore, there is a need for improved techniques and mechanisms for optimizing power used in an integrated circuit.